Memory system and operating method thereof

ABSTRACT

A memory system includes a memory device and a controller. The memory device includes a memory cell array including a normal memory cell area and a redundancy memory cell area, the redundancy memory cell area having a replacement memory cell region and a reserved memory cell region; a register suitable for generating a first signal indicating existence of the reserved memory cell region; and a fuse unit suitable for activating the reserved memory cell region based on the first signal. The controller assigns an address for accessing a reserved memory cell of the reserved memory cell region based on the first signal. A replacement memory cell in the replacement memory cell region replaces a failed memory cell in the normal memory cell region, and the reserved memory cell in the reserved memory cell region remains without replacing any failed memory cell in the normal memory cell region.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of U.S. application Ser. No.16/044,322, filed Jul. 24, 2018, which claims priority under 35 U.S.C. §119(a) to Korean Patent Application No. 10-2017-0143429 filed on Oct.31, 2017, the disclosure of which is incorporated by reference herein inits entirety.

BACKGROUND 1. Field

Various embodiments of the present disclosure relate to a memory system.Particularly, embodiments relate to a memory system capable ofefficiently processing data, and an operating method thereof.

2. Description of the Related Art

The paradigm for computing environments moves toward ubiquitouscomputing which allows people or users to use their or commonly suppliedcomputing systems anytime and everywhere. In the era of ubiquitouscomputing, the demand for portable electronic devices, such as mobilephones, digital cameras, and laptop computers, is soaring. Such aportable electronic device generally includes a memory system using amemory device as a data storage device. The data storage device may beused as a main memory unit or an auxiliary memory unit of the portableelectronic device.

Since a data storage device using a memory device does not have amechanical driving unit (e.g., a mechanical arm with a read/write head)as compared with a hard disk device, it may have excellent stability anddurability. Also, the data storage device can have a quick data accessrate with low power consumption compared to the hard disk device. Thedata storage device having such advantages includes any of a UniversalSerial Bus (USB) memory device, a memory card having diverse interfaces,a Solid-State Drive (SSD), and the like.

A memory device may include a plurality of memory cells. As the processtechnology develops, the degree of integration of the memory deviceincreases, and thus the number of memory cells in the memory device maybe further increased.

If any one of these memory cells is defective, the memory device havingthe defective memory cell may not perform a normal operation and shouldbe discarded. However, as the process technology develops, defects occuronly in a small number of memory cells. Therefore, it is inefficientconsidering the yield of the product to dispose of a memory device as adefective product because of a small number of defective memory cells inthe memory device. Accordingly, in order to compensate for thisinefficiency, a memory device may include redundancy memory cells inaddition to normal memory cells.

When a defect occurs in a normal memory cell, a redundancy memory cellmay replace a defective normal memory cell, that is, a failed memorycell. A redundancy memory cell replaced with a failed memory cell amongredundancy memory cells is called a replaced memory cell. Otherredundancy memory cells that remain not replaced with failed memorycells are referred to as reserved memory cells. For an efficient memorydevice operation, a method is needed to properly use the reserved memorycells.

SUMMARY

Various embodiments of the present disclosure are directed to a memorysystem capable of efficiently using redundancy memory cells and anoperating method thereof.

In accordance with an embodiment of the present invention, a memorysystem may include a memory device including: a memory cell arrayincluding a normal memory cell area and a redundancy memory cell area,the redundancy memory cell area having a replacement memory cell regionand a reserved memory cell region; a register suitable for generating afirst signal indicating existence of the reserved memory cell region;and a fuse unit suitable for activating the reserved memory cell regionbased on the first signal; and a controller suitable for assigning anaddress for accessing a reserved memory cell of the reserved memory cellregion based on the first signal, wherein a replacement memory cell inthe replacement memory cell region replaces a failed memory cell in thenormal memory cell region, and the reserved memory cell in the reservedmemory cell region remains without replacing any failed memory cell inthe normal memory cell region.

In accordance with an embodiment of the present invention, an operatingmethod of a memory system may include generating a first signalindicating existence of a reserved memory cell region in a memory cellarray included in a memory device; assigning an address for accessing areserved memory cell in the reserved memory cell region based on thefirst signal; activating the reserved memory cell region based on thefirst signal; and controlling the memory device based on the addressassigned to the reserved memory cell, wherein the memory cell arrayincludes a redundancy memory cell area and a normal memory cell area,and wherein the redundancy memory cell area includes a replacementmemory cell region and the reserved memory cell region, the replacementmemory cell region including a replacement memory cell for replacing afailed memory cell in the normal memory cell area, the reserved memorycell region including the reserved memory cell that remains withoutreplacing any failed normal memory cell in the normal memory cell area.

BRIEF DESCRIPTION OF THE DRAWINGS

The description herein makes reference to the accompanying drawingswherein like reference numerals refer to like parts throughout theseveral views, and wherein:

FIG. 1 is a block diagram illustrating a data processing systemincluding a memory system in accordance with an embodiment of thepresent disclosure;

FIG. 2 is a schematic diagram illustrating a memory cell array of amemory device in accordance with an embodiment of the presentdisclosure;

FIG. 3 is a block diagram schematically illustrating a memory system inaccordance with an embodiment of the present disclosure;

FIG. 4 is a flowchart schematically illustrating an operation of amemory system in accordance with an embodiment of the presentdisclosure;

FIG. 5 is a flowchart schematically illustrating an operation of amemory system in accordance with an embodiment of the presentdisclosure; and

FIG. 6 is a flowchart schematically illustrating an operation of amemory system in accordance with an embodiment of the presentdisclosure.

DETAILED DESCRIPTION

Various embodiments of the present disclosure are described below inmore detail with reference to the accompanying drawings. The disclosuremay be embodied in different other embodiments, forms, and variationsthereof, and should not be construed as being limited to the embodimentsset forth herein. Rather, the described embodiments are provided so thatthis disclosure will be thorough and complete, and will fully convey thedisclosure to those skilled in the art to which this invention pertains.Throughout the disclosure, like reference numerals refer to like partsthroughout the various figures and examples of the disclosure.

It will be understood that, although the terms “first,” “second,”“third,” and so on may be used herein to describe various elements,these elements are not limited by these terms. These terms are used todistinguish one element from another element. Thus, a first elementdescribed below could also be termed as a second or third elementwithout departing from the spirit and scope of the present invention.

The drawings are not necessarily to scale and, in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments. When an element is referred to as beingconnected or coupled to another element, it should be understood thatthe former can be directly connected or coupled to the latter, orelectrically connected or coupled to the latter via an interveningelement therebetween.

It will be further understood that when an element is referred to asbeing “connected to,” or “coupled to” another element, it may bedirectly on, connected to, or coupled to the other element, or one ormore intervening elements may be present. In addition, it will also beunderstood that when an element is referred to as being “between” twoelements, it may be the only element between the two elements, or one ormore intervening elements may also be present.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the presentinvention.

As used herein, singular forms are intended to include the plural formsas well, unless the context clearly indicates otherwise.

It will be further understood that the terms “comprises,” “comprising,”“includes,” and “including” when used in this specification, specify thepresence of the stated elements and do not preclude the presence oraddition of one or more other elements. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items.

Unless otherwise defined, all terms including technical and scientificterms used herein have the same meaning as commonly understood by one ofordinary skill in the art to which the present invention belongs in viewof the present disclosure. It will be further understood that terms,such as those defined in commonly used dictionaries, should beinterpreted as having a meaning that is consistent with their meaning inthe context of the present disclosure and the relevant art and will notbe interpreted in an idealized or overly formal sense unless expresslyso defined herein.

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Thepresent invention may be practiced without some or all of these specificdetails. In other instances, well-known process structures and/orprocesses have not been described in detail in order not tounnecessarily obscure the present invention.

It is also noted, that in some instances, as would be apparent to thoseskilled in the relevant art, a feature or element described inconnection with one embodiment may be used singly or in combination withother features or elements of another embodiment, unless otherwisespecifically indicated.

FIG. 1 is a block diagram illustrating a data processing system 100 inaccordance with an embodiment of the present disclosure.

Referring to FIG. 1, the data processing system 100 may include a host102 operatively coupled to a memory system 110.

The host 102 may include, for example, a portable electronic device,such as a mobile phone, an MP3 player, or a laptop computer, or anelectronic device, such as a desktop computer, a game player, a TV, aprojector, or the like.

The memory system 110 may perform a specific function or operation inresponse to a request from the host 102, and may store data to beaccessed by the host 102. The memory system 110 may be used as a mainmemory system or an auxiliary memory system of the host 102. The memorysystem 110 may be implemented with any one of various types of storagedevices, which may be electrically coupled with the host 102, accordingto a protocol of a host interface. Examples of the storage devicesinclude a solid state drive (SSD), a multimedia card (MMC), an embeddedMMC (eMMC), a reduced size MMC (RS-MMC) or micro-MMC, a secure digital(SD) card, a mini-SD or micro-SD, a universal serial bus (USB) storagedevice, a universal flash storage (UFS) device, a compact flash (CF)card, a smart media (SM) card, a memory stick, and the like.

The storage device for the memory system 110 may be implemented with avolatile memory device, such as any of a dynamic random access memory(DRAM) and a static RAM (SRAM), and/or a nonvolatile memory device suchas any of a read only memory (ROM), a mask ROM (MROM), a programmableROM (PROM), an erasable programmable ROM (EPROM), an electricallyerasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), aphase-change RAM (PRAM), a magneto-resistive RAM (MRAM), a resistive RAM(RRAM), and a flash memory.

The memory system 110 may include a memory device 150, which stores datato be accessed by the host 102, and a controller 130, which may controlan operation for storing data in the memory device 150.

The controller 130 and the memory device 150 may be integrated into asingle semiconductor device, which may be any of the various types ofmemory systems described above.

The memory system 110 may be configured as a part of a computer, anultra-mobile PC (UMPC), a workstation, a net-book, a personal digitalassistant (PDA), a portable computer, a web tablet, a tablet computer, awireless phone, a mobile phone, a smart phone, an e-book, a portablemultimedia player (PMP), a portable game player, a navigation system, ablack box, a digital camera, a digital multimedia broadcasting (DMB)player, a 3D television, a smart television, a digital audio recorder, adigital audio player, a digital picture recorder, a digital pictureplayer, a digital video recorder, a digital video player, a storageconfiguring a data center, a device capable of transmitting andreceiving information under a wireless environment, one of variouselectronic devices configuring a home network, any of various electronicdevices configuring a computer network, any of various electronicdevices configuring a telematics network, a radio frequencyidentification (RFID) device, or any of various components configuring acomputing system.

The memory device 150 may be a nonvolatile memory device, and may retaindata stored therein even when an electrical power is not supplied. Thememory device 150 may store data provided from the host 102 in a writeoperation, and provide data stored therein to the host 102 in a readoperation. The memory device 150 may include a plurality of memoryblocks 152 to 156, each of the memory blocks 152 to 156 may include aplurality of pages. Each of the plurality of pages may include aplurality of memory cells to which a corresponding one of a plurality ofword lines (WL) is electrically coupled.

The controller 130 may control overall operations of the memory device150, such as read, write, program, and erase operations. The controller130 may control the memory device 150 in response to a request from thehost 102. The controller 130 may provide data, read from the memorydevice 150, to the host 102, and/or may store data, provided by the host102, into the memory device 150.

The controller 130 may include a host interface (I/F) unit 132, aprocessor 134, an error correction code (ECC) unit 138, a powermanagement unit (PMU) 140, a memory device controller such as a memoryinterface (I/F) unit 142, and a memory 144, which are operativelycoupled to each other through an internal bus.

The host interface unit 132 may process requests and data provided bythe host 102, and may communicate with the host 102 through at least oneof various interface protocols such as a universal serial bus (USB), amultimedia card (MMC), peripheral component interconnect-express(PCI-E), a small computer system interface (SCSI), a serial-attachedSCSI (SAS), a serial advanced technology attachment (SATA), a paralleladvanced technology attachment (PATA), a small computer system interface(SCSI), an enhanced small disk interface (ESDI), and integrated driveelectronics (IDE). The host interface unit 132 may be driven by afirmware that is referred to as a “host interface layer (HIL).”

The ECC unit 138 may detect and correct errors in data read from thememory device 150 during a read operation. When the number of error bitsis greater than or equal to a threshold number of correctable errorbits, the ECC unit 138 may not correct the error bits, but may output anerror correction fail signal indicating a failure in correcting theerror bits.

The ECC unit 138 may perform an error correction operation based on acoded modulation such as a low density parity check (LDPC) code, aBose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS)code, a convolution code, a recursive systematic code (RSC), atrellis-coded modulation (TCM), a Block coded modulation (BCM),or acombination thereof. The ECC unit 138 may include all or some ofcircuits, modules, systems, or devices for performing the errorcorrection operation based on at least one of the above described codes.

The PMU 140 may provide power for operating the controller 130 andmanage the power of the controller 130.

The memory interface unit 142 may serve as an interface for handlingcommands and data transferred between the controller 130 and the memorydevice 150, so as to allow the controller 130 to control the memorydevice 150 in response to a request from the host 102. The memoryinterface unit 142 may generate a control signal for controlling thememory device 150, and may process data to be written into or outputtedfrom the memory device 150 under the control of the processor 134, whenthe memory device 150 is a flash memory and, in particular, when thememory device 150 is a NAND flash memory.

The memory 144 may serve as a working memory of the memory system 110,and may store temporary or transactional data for operating or drivingthe memory system 110. The controller 130 may control the memory device150 in response to a request from the host 102. The controller 130 maydeliver data read from the memory device 150 to the host 102, may storedata from the host 102 in the memory device 150. The memory 144 may beused to store data required for the controller 130 and the memory device150 in order to perform the read and write operations of the memorydevice 150.

The memory 144 may be implemented with a volatile memory. The memory 144may be implemented with a static random access memory (SRAM) or adynamic random access memory (DRAM). Although FIG. 1 illustrates thememory 144 that is disposed within the controller 130, embodiments arenot limited thereto. That is, the memory 144 may be located inside oroutside the controller 130. In another embodiment, the memory 144 may beembodied by an external volatile memory having a memory interface thattransfers data and/or signals between the memory 144 and the controller130.

The processor 134 may control the overall operations of the memorysystem 110. The processor 134 may drive or execute a firmware to controlthe overall operations of the memory system 110. The firmware may bereferred to as a flash translation layer (FTL).

A FTL may perform an operation as an interface between the host 102 andthe memory device 150. The host 102 may transmit requests for write andread operations to the memory device 150 through the FTL.

The FTL may manage operations such as address mapping, garbagecollection, wear-leveling, and so forth. Particularly, the FTL may storemapping data. Therefore, the controller 130 may perform an addressmapping operation by mapping a logical address, which is provided by thehost 102, to a physical address of the memory device 150 through the useof the mapping data. Also, through the address mapping operation basedon the mapping data, when the controller 130 updates data on aparticular page, the controller 130 may program new data on anotherempty page, and may invalidate old data on the particular page, due to acharacteristic of a flash memory device that is the memory device 150.Further, the controller 130 may store mapping data for the new data intothe FTL.

The processor 134 may be implemented with a microprocessor or a centralprocessing unit (CPU). The memory system 110 may include one or moreprocessors.

A management unit (not shown) may be included in the processor 134. Themanagement unit may perform bad block management of the memory device150. The management unit may find bad memory blocks included in thememory device 150 and perform bad block management on the bad memoryblocks. The bad memory block is a memory block that is in anunsatisfactory condition for further use. When the memory device 150 isa flash memory, for example, a NAND flash memory, a program failure mayoccur during a write operation, for example, during a program operation,due to characteristics of a NAND logic function. During the bad blockmanagement, data of the program-failed memory block or the bad memoryblock may be programmed into a new memory block. The bad memory blocksmay seriously aggravate the utilization efficiency of the memory device150 having a 3D stack structure and the reliability of the memory system110. To overcome these drawbacks, reliable bad block management isrequired.

Hereinafter, utilization of a reserved memory cell, which is not in useamong redundancy memory cells, will be described.

FIG. 2 is a schematic diagram illustrating a structure of the memorydevice 150 shown in FIG. 1 in accordance with an embodiment of thepresent disclosure.

The memory device 150 may include a memory cell array 290. The memorycell array 290 may be divided into a normal memory cell area 210 and aredundancy memory cell area 250. A plurality of normal memory cells maybe included in the normal memory cell area 210. The plurality of normalmemory cells may be coupled to a plurality of normal word lines NW0 toNWn, n being a positive integer. When one of the plurality of normalword lines NW0 to NWn is activated, data may be written into or read outfrom a multiplicity of normal memory cells coupled to the activatednormal word line.

A plurality of redundancy memory cells may be included in the redundancymemory cell area 250. The plurality of redundancy memory cells may becoupled to a plurality of redundancy word lines RW0 to RWm, m being apositive integer. When one of the plurality of redundancy word lines RW0to RWm is activated, data may be written into or read out from amultiplicity of redundancy memory cells coupled to the activatedredundancy word line.

The redundancy memory cell area 250 may be divided into a replacementmemory cell region 251 and a reserved memory cell region 253. Aplurality of replacement memory cells may be included in the replacementmemory cell region 251. The plurality of replacement memory cells may becoupled to a plurality of replacement word lines RpW0 to RpWI, I being apositive integer. The plurality of replacement memory cells may replacea corresponding number of failed normal memory cells. For example, whena replacement target memory cell or a failed memory cell, which iscoupled to the normal word line NWx, is detected in the normal memorycell area 210, the normal word line NWx coupled to the replacementtarget memory cell may be replaced by a replacement word line, e.g., thereplacement word line RpW1, in the replacement memory cell region 251. Aword line replacement operation of the memory system will be describedin detail with reference to FIG. 3.

A plurality of reserved memory cells may be included in the reservedmemory cell region 253. The plurality of reserved memory cells may becoupled to a plurality of reserved word lines RmW0 to RmWk, k being apositive integer. The plurality of reserved memory cells of the reservedmemory cell region 253 are not used for replacing failed memory cells,and thus they may be wasted. That is, in the redundancy memory cell area250, the remaining region other than the replacement memory cell region251 in which the plurality of replacement memory cells are replaced withfailed memory cells in the normal memory cell area 210 may be thereserved memory cell region 253. Therefore, the size of the reservedmemory cell region 253 may be determined depending on a number of failedmemory cells in the normal memory cell area 210. For example, when it isassumed that the redundancy memory cell area 250 occupies 3% of thememory cell array 290 1% of the memory cell array 290 is assigned as thereplacement memory cell region 251 including the plurality ofreplacement memory cells that are replaced with failed memory cells, 2%of the memory cell array 290 remains as the reserved memory cell region253. The reserved memory cell region 253 may be wasted. However, inaccordance with an embodiment of the present disclosure, the reservedmemory cell region 253 may be utilized without being wasted.

FIG. 3 is a block diagram schematically illustrating the memory system110 shown in FIG. 1 in accordance with an embodiment of the presentdisclosure.

Referring to FIG. 3, the memory system 110 includes the controller 130and the memory device 150. The controller 130 may control the memorydevice 150 by providing the memory device 150 with an address ADDR, acommand CMD, a DQ signal DQ, and a clock signal CLK.

The memory device 150 may include a memory device controller 300, a fuseunit 350, a cell array power management unit (PMU) 370, and the memorycell array 290 shown in FIG. 2. The memory device controller 300 mayinclude a register 330 and may communicate with each of the fuse unit350, the cell array power management unit 370, and the memory cell array290.

The register 330 may identify the redundancy memory cell area 250 of thememory cell array 290. The register 330 may identify each of thereplacement memory cell region 251 and the reserved memory cell region253 in the redundancy memory cell area 250. The register 330 may firstidentify the redundancy memory cell area 250 and may generate a firstsignal indicating existence of the redundancy memory cell area 250. Inorder to activate a plurality of redundancy memory cells, the register330 may re-set Mode Register Set (MRS) commands or may generateaddresses for accessing the plurality of redundancy memory cells byactivating internal circuits of the memory device 150.

The MRS commands may include commands for setting operations of thememory device 150 and commands for performing a read operation, a writeoperation, and a charging operation of the memory device 150.

Further, the register 330 may activate the fuse unit 350 to generateaddress combination for activating the plurality of redundancy memorycells, using addresses provided to the memory device 150. The register330 may provide the first signal to the controller 130. The controller130 may assign addresses for the plurality of redundancy memory cellsincluded in the redundancy memory cell area 250 based on the firstsignal.

The register 330 may generate a second signal for accessing the reservedmemory cell region 253. The register 330 may first identify the reservedmemory cell region 253 and may generate the second signal indicatingexistence of the reserved memory cell region 253. In order to activate aplurality of reserved memory cells in the reserved memory cell region253, the register 330 may re-set the Mode Register Set (MRS) commands ormay generate addresses for accessing the plurality of reserved memorycells by activating the internal circuits of the memory device 150.Further, the register 330 may activate the fuse unit 350 to generateaddress combination for activating the plurality of reserved memorycells, using addresses provided to the memory device 150. The register330 may provide the second signal to the controller 130. The controller130 may assign addresses for the plurality of reserved memory cellsincluded in the reserved memory cell region 253 based on the secondsignal.

The fuse unit 350 may receive the first and second signals, addressestransferred from the controller 130, and activation signals foractivating the plurality of redundancy memory cells and the plurality ofreserved memory cells from the register 330. The fuse unit 350 mayactivate the plurality of redundancy memory cells included in theredundancy memory cell area 250, and particularly, may activate theplurality of reserved memory cells included in the reserved memory cellregion 253 and the plurality of reserved word lines RmW0 to RmWk coupledto the plurality of reserved memory cells, based on the first and secondsignals, the addresses transferred from the controller 130, and theactivation signals for activating the plurality of redundancy memorycells and the plurality of reserved memory cells.

The memory cell array power management unit 370 may separately managepower of the normal memory cell area 210 and power of the redundancymemory cell area 250 based on control signals provided from the memorydevice controller 300. Particularly, the memory cell array powermanagement unit 370 may separately manage power of the reserved memorycell region 253. Therefore, the memory cell array power management unit370 may turn off the power of the reserved memory cell region 253 duringan operation for a request, which does not use the plurality of reservedmemory cells.

FIG. 4 is a flowchart schematically illustrating an operation of thememory system 110 shown in FIG. 3 in accordance with an embodiment ofthe present disclosure. FIG. 4 shows an operation of utilizing theplurality of reserved memory cells included in the reserved memory cellregion 253. The operation shown in FIG. 4 will be described withreference to FIG. 3.

At step S401, the register 330 may identify the reserved memory cellregion 253 as well as the redundancy memory cell area 250. The size ofthe reserved memory cell region 253 may be changed according to a typeof the memory system 110.

When the memory device 150 does not include a reserved memory cellregion, i.e., the reserved memory cell region is not identified (“No” atstep S401), the memory system 110 may terminate a process withoutperforming any particular operation relating to the reserved memory cellregion.

When the reserved memory cell region 253 is identified (“Yes” at stepS401), the memory system 110 may perform an operation for utilizing thereserved memory cell region 253.

When the register 330 identifies the reserved memory cell region 253, atstep S403, the register 330 may generate the second signal indicatingexistence of the reserved memory cell region 253. As described above,the second signal may be provided to fuse unit 350. Also, the secondsignal may be provided to the controller 130.

At step S405, the controller 130 may assign addresses for accessing theplurality of reserved memory cells included in the reserved memory cellregion 253 based on the second signal, and may provide the generatedaddresses to the memory device 150.

At step S407, the fuse unit 350 may activate the plurality of reservedmemory cells included in the reserved memory cell region 253 based onthe activation signals provided from the register 330 and the addressesprovided from the controller 130. The activated plurality of reservedmemory cells can be used for a particular operation of the memory system110.

Accordingly, the controller 130 may use all of the normal memory cellarea 210, the replacement memory cell region 251, and the reservedmemory cell region 253 as a memory space of the memory device 150.

FIG. 5 is a flowchart schematically illustrating an operation of thememory system 110 shown in FIG. 3 in accordance with another embodimentof the present disclosure. FIG. 5 shows an operation of processing arequest according to whether the request utilizes the plurality ofreserved memory cells included in the reserved memory cell region 253 ornot. The operation shown in FIG. 5 will be described with reference toFIG. 3.

At step S501, the controller 130 may analyze a request provided from anexternal device, e.g., the host 102 shown in FIG. 1. The controller 130may determine whether the request uses the reserved memory cell region253 in the memory device 150.

When the request does not use the reserved memory cell region 253 (“No”at step S501), the memory cell array power management unit 370 may turnoff power of the reserved memory cell region 253 under the control ofthe controller 130 at step S503.

When it is determined that the request uses the reserved memory cellregion 253 (“Yes” at step S501), the memory cell array power managementunit 370 may turn on the power of the reserved memory cell region 253under the control of the controller 130 at step S505.

FIG. 6 is a flowchart schematically illustrating an operation of thememory system 110 shown in FIG. 3 in accordance with another embodimentof the present disclosure. FIG. 6 shows an operation of overcoming therow hammering. The row hammering may occur on a neighboring word line ofa particular word line when a request processing operation is repeatedlyperformed to the particular word line.

At step S601, the controller 130 may count the number of access requestsactivating each of the plurality of word lines included in the memorydevice 150. Particularly, the controller 130 may count the number ofaccess requests activating each of the plurality of normal word linesNW0 to NWn in the normal memory cell area 210, and may detect a wordline corresponding to the number of access requests that is greater thana predetermined threshold value, among the plurality of normal wordlines NW0 to NWn in the normal memory cell area 210.

When there is no word line, corresponding to the number of accessrequests that is greater than the predetermined threshold value, amongthe plurality of normal word lines NW0 to NWn in the normal memory cellarea 210 (“No” at step S601), the memory system 110 may terminate theprocess.

When there is detected a word line, corresponding to the number ofaccess requests that is greater than the predetermined threshold value,among the plurality of normal word lines NW0 to NWn in the normal memorycell region 210 (“Yes” at step S601), the controller 130 may control thememory device 150 to move data stored in a multiplicity of normal memorycells coupled to the detected word line into a multiplicity of reservedmemory cells coupled to a word line selected from the plurality ofreserved word lines RmW0 to RmWk in the reserved memory cell region 253.The controller 130 may control the memory device 150 to copy the datastored in the multiplicity of normal memory cells coupled to thedetected word line into the multiplicity of reserved memory cellscoupled to the selected reserved word line, and may assign addresses foraccessing the multiplicity of reserved memory cells coupled to theselected reserved word line.

As described above, the controller 130 of the memory system 110 mayimprove the reliability issue such as the row hammering by using thereserved memory cell region 253. That is, in the memory system 110, wordlines in the normal memory cell area 210 are monitored before a problemoccurs by the row hammering, an address for activating a first word lineon which the problem may occur due to the row hammering is replaced withan address for activating a second word line in the reserved memory cellregion 253, and data stored in normal memory cells coupled to the firstword line is copied and moved to reserved memory cells coupled to thesecond word line. The reserved memory cells are used to prevent the rowhammering from occurring in the memory system 110.

Although not illustrated, the memory system 110 in accordance with anembodiment of the present disclosure may include a plurality of memorydevices. Each of the plurality of memory devices may correspond to thememory device 150 shown in FIG. 3. The controller 130 may control eachof the plurality of memory devices.

In accordance with the various embodiments of the present disclosure, amemory space recognized as substantial may be increased by replacingfailed memory cells in the normal memory cell area 210 with redundancymemory cells in the redundancy memory cell area 250 and by identifyingthe reserved memory cell region 253 of the redundancy memory cell region250 and using the reserved memory cell region 253 for other usage. Also,in accordance with the various embodiments of the present disclosure,characteristics of the memory system 110 may be improved by increasingan amount of memory cells practically used. That is, when the capacityof a memory assigned for processing a request is insufficient, thecontroller 130 may additionally assign a plurality of reserved memorycells to process the request. Further, in accordance with the variousembodiments of the present disclosure, the reliability of the memorysystem 110 may be improved by using the reserved memory cell region 253to remove a reliability issue such as the row hammering.

While the present invention has been described with respect to specificembodiments, it will be apparent to those skilled in the art thatvarious changes and modifications may be made without departing from thespirit and scope of the invention as determined in the following claims.

What is claimed is:
 1. A memory system comprising: a plurality of memory devices including first and second memory devices, the first memory device having a memory cell array and a device controller, the memory cell array including a normal memory cell area and a redundancy memory cell area, the device controller being configured to generate a first signal associated with the redundancy memory cell area; and a memory controller provided external to the first memory device and configured to enable accessing of a redundancy memory cell of the redundancy memory cell area of the first memory device based on the first signal.
 2. The memory system of claim 1, wherein the memory controller is configured to assign a first address for accessing the redundancy memory cell and control the first memory device to activate the redundancy memory cell based on the first address.
 3. The memory system of claim 2, wherein the first memory device further comprises a fuse unit configured to activate the redundancy memory cell based on the first address.
 4. The memory system of claim 3, wherein the first signal is provided to the fuse unit together with a Mode Register Set (MRS) signal.
 5. The memory system of claim 4, wherein the fuse unit activates the redundancy memory cell based on the first signal, the MRS signal, and the first address.
 6. The memory system of claim 1, wherein the first memory device further comprises a memory cell array power management unit that separately manages power of the redundancy memory cell area from power of the normal memory cell area.
 7. The memory system of claim 6, wherein the memory cell array power management unit turns off the power of the redundancy memory cell area unless a request uses the redundancy memory cell area.
 8. The memory system of claim 1, wherein the redundancy memory cell area includes a replacement memory cell region and a reserved memory cell region, wherein the device controller generates a second signal associated with the reserved memory cell region, and the memory controller assigns a second address for accessing a reserved memory cell of the reserved memory cell region based on the second signal, and wherein a replacement memory cell in the replacement memory cell region replaces a failed memory cell in the normal memory cell area, and the reserved memory cell in the reserved memory cell region remains without replacing any failed memory cell in the normal memory cell area.
 9. The memory system of claim 8, wherein the memory controller monitors a number of access requests activating each of a plurality of word lines in the first memory device.
 10. The memory system of claim 9, wherein the memory controller controls the first memory device to copy data stored in memory cells coupled to a first word line, for which the number of access requests is greater than a threshold value, into memory cells coupled to a second word line of the reserved memory cell region, and wherein the memory controller assigns an address for activating the first word line to the second word line.
 11. The memory system of claim 8, wherein the first memory device further includes a memory cell array power management unit that separately manages power of the reserved memory cell region from power of the normal memory cell area, and the memory cell array power management unit turns off the power of the reserved memory cell region unless a request uses the reserved memory cell region, and wherein, when a capacity of a memory assigned for processing a request is insufficient, the memory controller assigns the reserved memory cell to process the request.
 12. The memory system of claim 1, wherein the second memory device has a memory cell array and a device controller, the second memory cell array including a normal memory cell area and a redundancy memory cell area, the second device controller being configured to generate a third signal associated with the redundancy memory cell area of the second memory cell array, and wherein the memory controller is provided external to the second memory device and configured to enable accessing of a redundancy memory cell of the redundancy memory cell area of the second memory device based on the third signal.
 13. A method for operating a memory system, the method comprising: receiving, by a memory controller, a first signal associated with a redundancy memory cell area in a memory cell array of a first memory device, the memory cell array of the first memory device including a normal memory cell area and the redundancy memory cell area, the memory controller being provided external to the first memory device; assigning, by the memory controller, a first address for accessing a redundancy memory cell in the redundancy memory cell area of the first memory device based on the first signal; and controlling, by the memory controller, the first memory device to activate the redundancy memory cell of the first memory device based on the first address.
 14. The method of claim 13, further comprising storing the first address assigned to the redundancy memory cell in a fuse unit of the memory device, wherein the first signal is generated by the first memory device.
 15. The method of claim 14, wherein the first signal is provided to the fuse unit along with a Mode Register Set (MRS) signal, and the activating of the redundancy memory cell includes activating the redundancy memory cell based on the first signal, the MRS signal, and the first address assigned to the redundancy memory cell.
 16. The method of claim 13, wherein the redundancy memory cell area includes a replacement memory cell region and a reserved memory cell region, the method further comprising: receiving, by the memory controller, a second signal associated with the reserved memory cell region in the memory cell array; assigning, by the memory controller, a second address for accessing a reserved memory cell in the reserved memory cell region based on the second signal; and controlling, by the memory controller, the first memory device to activate the reserved memory cell based on the second address, wherein a replacement memory cell in the replacement memory cell region replaces a failed memory cell in the normal memory cell area, and the reserved memory cell in the reserved memory cell region remains without replacing any failed memory cell in the normal memory cell area.
 17. The method of claim 16, further comprising monitoring, by the memory controller, a number of access requests activating each of a plurality of word lines in the first memory device, wherein the controlling of the first memory device comprises controlling the first memory device to copy data stored in memory cells coupled to a first word line, for which the number of access requests is greater than a threshold value, into memory cells coupled to a second word line of the reserved memory cell region, and wherein the method further comprises assigning, by the memory controller, an address for activating the first word line to the second word line.
 18. The method of claim 16, further comprising turning off, by the memory controller, power of the reserved memory cell region unless a request uses the reserved memory cell region.
 19. The method of claim 16, wherein the controlling of the first memory device comprises controlling the first memory device to assign the reserved memory cell to process a request when a capacity of a memory assigned for processing the request is insufficient.
 20. The method of claim 13, further comprising: receiving, by the memory controller, a third signal associated with a redundancy memory cell area in a memory cell array of a second memory device, the memory cell array of the second memory device including a normal memory cell area and the redundancy memory cell area, the memory controller being provided external to the second memory device; assigning, by the memory controller, a third address for accessing a redundancy memory cell in the redundancy memory cell area of the second memory device based on the third signal; and controlling, by the memory controller, the second memory device to activate the redundancy memory cell of the second memory device based on the third address. 